5 #ifndef _RTE_ETH_CTRL_H_ 6 #define _RTE_ETH_CTRL_H_ 29 RTE_ETH_FILTER_NONE = 0,
30 RTE_ETH_FILTER_MACVLAN,
31 RTE_ETH_FILTER_ETHERTYPE,
32 RTE_ETH_FILTER_FLEXIBLE,
34 RTE_ETH_FILTER_NTUPLE,
35 RTE_ETH_FILTER_TUNNEL,
38 RTE_ETH_FILTER_L2_TUNNEL,
39 RTE_ETH_FILTER_GENERIC,
85 #define RTE_ETHTYPE_FLAGS_MAC 0x0001 86 #define RTE_ETHTYPE_FLAGS_DROP 0x0002 93 struct rte_eth_ethertype_filter { 100 #define RTE_FLEX_FILTER_MAXLEN 128 101 #define RTE_FLEX_FILTER_MASK_SIZE \ 102 (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT) 134 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001 135 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 136 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 137 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 138 #define RTE_NTUPLE_FLAGS_PROTO 0x0010 139 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 141 #define RTE_5TUPLE_FLAGS ( \ 142 RTE_NTUPLE_FLAGS_DST_IP | \ 143 RTE_NTUPLE_FLAGS_SRC_IP | \ 144 RTE_NTUPLE_FLAGS_DST_PORT | \ 145 RTE_NTUPLE_FLAGS_SRC_PORT | \ 146 RTE_NTUPLE_FLAGS_PROTO) 148 #define RTE_2TUPLE_FLAGS ( \ 149 RTE_NTUPLE_FLAGS_DST_PORT | \ 150 RTE_NTUPLE_FLAGS_PROTO) 152 #define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F 159 struct rte_eth_ntuple_filter { 183 #define ETH_TUNNEL_FILTER_OMAC 0x01 184 #define ETH_TUNNEL_FILTER_OIP 0x02 185 #define ETH_TUNNEL_FILTER_TENID 0x04 186 #define ETH_TUNNEL_FILTER_IMAC 0x08 187 #define ETH_TUNNEL_FILTER_IVLAN 0x10 188 #define ETH_TUNNEL_FILTER_IIP 0x20 190 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \ 191 ETH_TUNNEL_FILTER_IVLAN) 192 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \ 193 ETH_TUNNEL_FILTER_IVLAN | \ 194 ETH_TUNNEL_FILTER_TENID) 195 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \ 196 ETH_TUNNEL_FILTER_TENID) 197 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \ 198 ETH_TUNNEL_FILTER_TENID | \ 199 ETH_TUNNEL_FILTER_IMAC) 222 uint32_t ipv6_addr[4];
235 RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
236 RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
237 RTE_ETH_GLOBAL_CFG_TYPE_MAX,
251 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 252 #define RTE_ETH_INSET_SIZE_MAX 128 257 enum rte_eth_input_set_field { 258 RTE_ETH_INPUT_SET_UNKNOWN = 0,
261 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
262 RTE_ETH_INPUT_SET_L2_DST_MAC,
263 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
264 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
265 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
268 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
269 RTE_ETH_INPUT_SET_L3_DST_IP4,
270 RTE_ETH_INPUT_SET_L3_SRC_IP6,
271 RTE_ETH_INPUT_SET_L3_DST_IP6,
272 RTE_ETH_INPUT_SET_L3_IP4_TOS,
273 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
274 RTE_ETH_INPUT_SET_L3_IP6_TC,
275 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
276 RTE_ETH_INPUT_SET_L3_IP4_TTL,
277 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
280 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
281 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
282 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
283 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
284 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
285 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
286 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
289 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
290 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
291 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
292 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
293 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
296 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
297 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
298 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
299 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
300 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
301 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
302 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
303 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
305 RTE_ETH_INPUT_SET_DEFAULT = 65533,
306 RTE_ETH_INPUT_SET_NONE = 65534,
307 RTE_ETH_INPUT_SET_MAX = 65535,
314 RTE_ETH_INPUT_SET_OP_UNKNOWN,
317 RTE_ETH_INPUT_SET_OP_MAX
428 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
429 RTE_FDIR_TUNNEL_TYPE_NVGRE,
430 RTE_FDIR_TUNNEL_TYPE_VXLAN,
488 RTE_ETH_FDIR_ACCEPT = 0,
490 RTE_ETH_FDIR_PASSTHRU,
556 RTE_ETH_PAYLOAD_UNKNOWN = 0,
561 RTE_ETH_PAYLOAD_MAX = 8,
611 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t)) 612 #define RTE_FLOW_MASK_ARRAY_SIZE \ 613 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) 630 uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
672 RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
675 RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
702 RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
709 RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
712 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ 713 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) 726 uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
728 uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
#define RTE_ETH_FDIR_MAX_FLEXLEN
uint32_t flex_payload_unit
rte_eth_fdir_filter_info_type
#define RTE_FLEX_FILTER_MAXLEN
uint32_t max_flex_payload_segment_num
uint32_t max_flex_bitmask_num
uint32_t flex_bitmask_unit
enum rte_mac_filter_type filter_type
uint16_t flex_payload_limit
#define RTE_ETH_INSET_SIZE_MAX
uint8_t mac_addr_byte_mask
#define RTE_FLEX_FILTER_MASK_SIZE
rte_eth_hash_filter_info_type